Adrian Molofsky
Adrian Molofsky

Adrian Molofsky

Artificial Intelligence, Systems

Biography

I am currently a research resident at Redwood Research, where I build infrastructure for interpretability research on large language models.

I received my M.S. and B.S. in Computer Science from Stanford University, with a minor in Electrical Engineering, specializing in artificial intelligence and systems. My graduate work focused on machine learning systems and my undergraduate work focused on performance engineering.

I spent a year as a machine learning researcher at Stanford and as a data science intern at Gladstone Institutes. Before that, I was a research intern twice at UC San Francisco.

In my free time, I enjoy spending time outdoors backpacking, birdwatching, and golfing, as well as playing strategy games such as chess, crossword, and poker.

Education

Stanford University
M.S. Computer Science
Artificial Intelligence Track
2024 - 2026
Stanford University
B.S. Computer Science, Minor in Electrical Engineering
Systems Track
2020 - 2024

Experience

Redwood Research
Research Resident
February 2026 - Present
Stanford University
Machine Learning Researcher
June 2024 - September 2025
Gladstone Institutes
Data Science Intern
June 2024 - September 2024
University of California, San Francisco
Research Intern
June 2023 - September 2023
University of California, San Francisco
Research Intern
June 2019 - September 2019

Projects

Deep Neural Network Accelerator

Developed a ResNet-18 hardware accelerator through digital design, verification, synthesis, and physical design.

Transformer Language Model

Built a language model with custom GPU kernels, distributed data parallel training, and optimizer state sharding.

Graph Neural Network Recommender System

Built a graph neural network user-article recommender system on the Microsoft News Dataset (MIND).

View Report →

Price-Pure Prediction of Daily Price Changes in Binary Event Contracts

Forecasted daily price changes in binary event contracts backtesting on 10K+ time-series samples from Kalshi.

View Code →

Comparing Reinforcement Learning Methods for Sparse vs. Dense Rewards

Benchmarked PPO, DDPG, SAC, and TD3 policies on a 1,000 sample states from the Point Maze environment.

View Code →

Micropolygon Rasterization Accelerator

Designed a rasterization hardware accelerator with micropolygon bounding, edge traversal, and backface culling.

Five-Stage Pipelined MIPS Processor

Developed a five-stage pipelined processor for the MIPS ISA with hazard detection, forwarding, and stall control.

Register Renaming in a RISC-V Processor

Implemented register renaming logic in a pipelined RISC-V processor to eliminate write after write and write after read hazards.

Performance Tradeoffs of Error-Correcting Codes within Network Routers

Benchmarked parity, checksum, and Hamming error-correcting codes in 8×8 2D Torus routers using BookSim.

Formalizing Intel's Remote Action Request

Defined Intel's Remote Action Request for remote TLB shootdowns through memory transiency models.

Cool Compiler

Developed a compiler for the Cool programming language with lexical analysis, parsing, semantic analysis, and MIPS code generation.

Pintos OS

Built an operating system with thread scheduling, user program execution, virtual memory, and file systems.